Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision
- Authors
- Lee, Kyeongho; Jeong, Jinho; Cheon, Sungsoo; Choi, Woong; Park, Jongsun
- Issue Date
- Jul-2020
- Publisher
- IEEE
- Keywords
- Bitline Computing; In-Memory Computing; Processing-In-memory; Read Disturb; Short Pulse WL
- Citation
- Proceedings - Design Automation Conference, v.2020-July, pp 1 - 6
- Pages
- 6
- Journal Title
- Proceedings - Design Automation Conference
- Volume
- 2020-July
- Start Page
- 1
- End Page
- 6
- URI
- https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/1132
- DOI
- 10.1109/DAC18072.2020.9218567
- ISSN
- 0738-100X
- Abstract
- This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL followed by BL boosting circuits, which can reduce BL computing delays. By per-forming carry-propagation between each near-memory circuit, bit-parallel complex computations are also enabled by iterating operations with low latency. In addition, reconfigurable bit-precision is also supported based on carry-propagation size. Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 0.9V with 5.2% of area overhead. The proposed architecture also achieves 0.68, 8.09 TOPS/W for the parallel addition and multiplication, respectively. In addition, the proposed work also supports a wide range of supply voltage, from 0.6V to 1.1V. © 2020 IEEE.
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