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Cited 18 time in webofscience Cited 4 time in scopus
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POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE

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dc.contributor.authorKim, Yoonjin-
dc.date.available2021-02-22T12:16:42Z-
dc.date.issued2013-03-
dc.identifier.issn0218-1266-
dc.identifier.issn1793-6454-
dc.identifier.urihttps://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/11330-
dc.description.abstractCoarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and exibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes - one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and exibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.-
dc.language영어-
dc.language.isoENG-
dc.publisherWORLD SCIENTIFIC PUBL CO PTE LTD-
dc.titlePOWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE-
dc.typeArticle-
dc.publisher.location싱가폴-
dc.identifier.doi10.1142/S0218126613500011-
dc.identifier.scopusid2-s2.0-84874035411-
dc.identifier.wosid000316911700001-
dc.identifier.bibliographicCitationJOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.22, no.3-
dc.citation.titleJOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS-
dc.citation.volume22-
dc.citation.number3-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordAuthorSystem-on-chip (SoC)-
dc.subject.keywordAuthorembedded systems-
dc.subject.keywordAuthordigital signal processing-
dc.subject.keywordAuthorcoarse-grained reconfigurable architecture (CGRA)-
dc.subject.keywordAuthorconfiguration cache-
dc.subject.keywordAuthorcontext word-
dc.identifier.urlhttps://www.worldscientific.com/doi/abs/10.1142/S0218126613500011-
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공과대학 (소프트웨어학부(첨단))
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