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Cache conscious trees on modern microprocessors

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dc.contributor.authorLee, Ig-Hoon-
dc.contributor.authorLee, Jae-Won-
dc.contributor.authorShim, Junho-
dc.contributor.authorLee, Sang-Goo-
dc.date.available2021-02-22T14:03:05Z-
dc.date.issued2010-01-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/13615-
dc.description.abstractRecent research shows that database performance can be significantly improved by the effective cache utilization of conventional microprocessors. Researchers have modified existing index structures into ones optimized for CPU cache performance in main memory database environments. The Cache Sensitive B +-Tree and recently developed Cache Sensitive T-Tree are the most well-known cache conscious index structures. In this paper, we present an experimental performance study to show how cache conscious trees perform on different types of modern CPU processors. We perform experiment evaluation on basic tree operations, search, range search, and insertion/deletion operation. © 2010 ACM.-
dc.format.extent5-
dc.language영어-
dc.language.isoENG-
dc.publisherACM digital library-
dc.titleCache conscious trees on modern microprocessors-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1145/2108616.2108668-
dc.identifier.scopusid2-s2.0-84863256662-
dc.identifier.bibliographicCitationProceedings of the 4th International Conference on Ubiquitous Information Management and Communication ICUIMC 10, pp 300 - 304-
dc.citation.titleProceedings of the 4th International Conference on Ubiquitous Information Management and Communication ICUIMC 10-
dc.citation.startPage300-
dc.citation.endPage304-
dc.type.docTypeConference Paper-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusCPU cache-
dc.subject.keywordPlusCST-tree-
dc.subject.keywordPlusindex structure-
dc.subject.keywordPlusmain memory-
dc.subject.keywordPlusmicroprocessor-
dc.subject.keywordPlusT-tree-
dc.subject.keywordPlusCommunication-
dc.subject.keywordPlusForestry-
dc.subject.keywordPlusInformation management-
dc.subject.keywordPlusMicroprocessor chips-
dc.subject.keywordPlusTrees (mathematics)-
dc.subject.keywordPlusCache memory-
dc.subject.keywordPlusCommunication-
dc.subject.keywordPlusData Bases-
dc.subject.keywordPlusForestry-
dc.subject.keywordPlusInformation Retrieval-
dc.subject.keywordPlusManagement-
dc.subject.keywordPlusMathematics-
dc.subject.keywordPlusTrees-
dc.subject.keywordAuthorCPU cache-
dc.subject.keywordAuthorCST-tree-
dc.subject.keywordAuthorindex structure-
dc.subject.keywordAuthormain memory-
dc.subject.keywordAuthormicroprocessor-
dc.subject.keywordAuthorT-tree-
dc.identifier.urlhttps://dl.acm.org/doi/10.1145/2108616.2108668-
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