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DCPA: approximate adder design exploiting dual carry prediction

Authors
Choi, WoongShim, MinseobSeok, HyelinKim, Yongtae
Issue Date
Dec-2021
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATION ENGINEERS
Keywords
approximate adder; dual carry prediction; energy efficiency
Citation
IEICE ELECTRONICS EXPRESS, v.18, no.23, pp.1 - 4
Journal Title
IEICE ELECTRONICS EXPRESS
Volume
18
Number
23
Start Page
1
End Page
4
URI
https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/146084
DOI
10.1587/elex.18.20210431
ISSN
1349-2543
Abstract
This letter presents a novel approximate adder that significantly improves computation accuracy by utilizing a dual carry prediction and error reduction scheme. In our experiments, the proposed adder improves mean error distance (MED) and mean relative error distance (MRED) by up to 58.6% and 58.5%, respectively, when compared with existing approximate adders. Also, when implemented in 65-nm CMOS technology, the proposed adder reduces area, delay, and power by 37%, 48%, and 41%, respectively, compared with the traditional adder. Furthermore, the effectiveness of our design over existing adders is investigated using a digital image processing application.
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