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Cache conscious trees: How do they perform on contemporary commodity microprocessors?
- Issue Date
- Aug-2007
- Publisher
- Springer Verlag
- Citation
- Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v.4705 LNCS, no.PART 1, pp 189 - 200
- Pages
- 12
- Journal Title
- Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
- Volume
- 4705 LNCS
- Number
- PART 1
- Start Page
- 189
- End Page
- 200
- ISSN
- 0302-9743
- Abstract
- Some index structures have been redesigned to minimize the cache misses and improve their CPU cache performances. The Cache Sensitive B+Tree and recently developed Cache Sensitive T-Tree are the most well-known cache conscious index structures. Their performance evaluations, however, were made in single core CPU machines. Nowadays even the desktop computers are equipped with multi-core CPU processors. In this paper, we present an experimental performance study to show how cache conscious trees perform on different types of CPU processors that are available in the market these days. © Springer-Verlag Berlin Heidelberg 2007.
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