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Efficient Reconfigurable Architecture to Accelerate Descriptor Extraction in SURF Algorithm

Authors
Kim, YoonjinJung, Haelim
Issue Date
Jun-2018
Publisher
IEEK PUBLICATION CENTER
Keywords
Computer vision; speeded-up robust features (SURF); hardware accelerator; reconfigurable architecture; descriptor extraction
Citation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.3, pp 396 - 401
Pages
6
Journal Title
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
Volume
18
Number
3
Start Page
396
End Page
401
URI
https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/4494
DOI
10.5573/JSTS.2018.18.3.396
ISSN
1598-1657
2233-4866
Abstract
Speeded-up robust features (SURF) is considered to be the most efficient feature extraction algorithm and it has been implemented in powerful hardware for real-time operation due to its characteristics of data-intensive computation of high complexity. Especially the computational load of the descriptor extraction procedure is very significant and the overall performance of SURF can be improved by speeding up the descriptor extraction step with increasing parallel hardware accelerators. However, simply increasing the hardware accelerators is burdensome because of causing significant area and power consumption. Therefore, in this paper, we propose a reconfigurable hardware architecture that enables achieving the maximum performance of the descriptor extraction step with making the best use of the existing accelerators without any additional ones. Experimental results show that the proposed architecture improves the performance of the descriptor extraction step by 21.51% similar to 47.31% with negligible area and small power overheads of less than 1% and 4% when compared with the existing hardware implementations of the SURF algorithm.
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Kim, Yoon Jin
공과대학 (소프트웨어학부(첨단))
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