ScholarWorks@숙명여자대학교

초록

This paper proposes a dual loop low-dropout regulator (LDO) for heavy load current (IL). The proposed LDO features a fast load transient response and wide output capacitor(CO) range. The proposed dynamic negative feedback loop(DNFL) enhances the transient response by reducing the under-shoot and widening the bandwidth. The transient response is improved further by the proposed dynamic G(m) boosting erroramplifier. The COrange gets wider thanks to the proposed DNFL,which introduces an additional zero in the feedback loop. Thezero secures stability in a wide COrange. The prototype ofthe proposed LDO is fabricated in a 0.5-mu m CMOS process.The input voltage (VIN) ranges from 2.7 to 4.2 V, while theoutput voltage (VO) ranges from 2.4 to 4.0 V. The maximum ILis 2 A. The prototype provides enough phase margin across aCOrange from 0 to 1 mu F. The measured results show a 68-mVundershoot with a load current of 2.5 A/1 mu s on a 0-mu F COcapacitor. When the COis 1 mu F under the same conditions, theproposed LDO features an undershoot of 13 mV. The proposedLDO achieves the best FoM among the state-of-the-art LDOswithout and with the off-chip CO. In cases where the off-chipCOis not employed, the achieved FoM is 5.228 ps<middle dot>V/mu m2. Whenusing the off-chip CO, the FoM is 0.624 ps/mu m2.

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