ScholarWorks@숙명여자대학교

초록

This paper presents a pseudo single-stage (PSS) amplifier with an adaptively varied medium impedance node to achieve an ultra-high slew rate (SR) and at the same time stable operation in a wide capacitive load range. Owing to the characteristics of the proposed technique, this amplifier achieves a 1.1-to-8.67 V/μs slew rate and a 0.01-to-1.66 MHz unity gain frequency over a 0.1-to-15 nF capacitive load (C L ) with an over 69° phase margin while consuming a total quiescent power of only 7.4 μW. This chip was fabricated in a 0.18 μm CMOS process with a silicon area of 0.0021 mm 2 .

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