Optimized Multiplier Architecture: Integrating Det/Pre-Encoder and Compound Gate

초록

The increasing demand for modern applications requiring large data processing has led to increased computational resource usage and higher power consumption. Therefore, there is a growing need to lighten the design of multipliers. In this paper, we propose a novel approach for the radix-4 Booth multiplier with a detect (Det)-encoder that identifies specific input pat-terns, reducing power consumption and transistor count. By utilizing the compound gates for the Det-encoder, the transistor count can be significantly reduced by 37.8% and power consumption by 28.6%, as demonstrated in a design implemented in 28nm CMOS technology.

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