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A Dynamic Power Transistor-Based CL-LDO with Wide Load Range and -53 dB PSRR Improvement
- Jin, Yunam;
- Gwon, Ayeon;
- Kim, Minseo;
- Noh, Jiwoo;
- Choi, Woong;
- ... Jeong, Junwon
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0초록
This paper presents a dynamic power transistor-based capacitor-less low-dropout (CL-LDO) regulator for a wide load range. The proposed adaptive DC level shifter enables the operation at the light load by adaptively providing the required VGS of the source follower regarding load. The dynamic power transistor (DPT) controls the non-dominant pole to ensure stability over a wide load range and improve PSRR. The proposed CL-LDO is implemented in a 45-nm CMOS process. The phase margin is improved from 14 deg to 79 deg at the light load condition (IL =10 μA). The PSRR improved by 53 dB. © 2023 IEEE.
키워드
-3dB bandwidth; CL-LDO; DC level shift; Dynamic Power Transistor; load regulation; PSRR; stability; Wide load range
- 제목
- A Dynamic Power Transistor-Based CL-LDO with Wide Load Range and -53 dB PSRR Improvement
- 저자
- Jin, Yunam; Gwon, Ayeon; Kim, Minseo; Noh, Jiwoo; Choi, Woong; Jeong, Junwon
- 발행일
- 2023-10
- 유형
- Conference paper
- 저널명
- Proceedings - International SoC Design Conference 2023, ISOCC 2023
- 페이지
- 37 ~ 38