DCPA: approximate adder design exploiting dual carry prediction

초록

This letter presents a novel approximate adder that significantly improves computation accuracy by utilizing a dual carry prediction and error reduction scheme. In our experiments, the proposed adder improves mean error distance (MED) and mean relative error distance (MRED) by up to 58.6% and 58.5%, respectively, when compared with existing approximate adders. Also, when implemented in 65-nm CMOS technology, the proposed adder reduces area, delay, and power by 37%, 48%, and 41%, respectively, compared with the traditional adder. Furthermore, the effectiveness of our design over existing adders is investigated using a digital image processing application.

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