ScholarWorks@숙명여자대학교

초록

This paper presents the implementation of a Resolution-Multiplied Time-to-Digital Converter (RM-TDC) and a Sub-harmonically Injection locked Phase-Locked Loop (SIPLL) based on a digital frequency loop to correct frequency offset. The proposed design performs frequency adjustment via a Sampled-Edge-Direction-Dependent Frequency Detector (SEDD-FD), achieving faster and more efficient frequency lock. Also, RM-TDC was used to detect the frequency offset in order to enhance jitter performance. This design has an integrated jitter of 676 fs, a phase noise of -114.26 dBc/Hz at 10 Mhz, occupies an area of 0.052 mm2, and consumes 2.43 mW. It is manufactured using a 65 nm CMOS process.

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