ScholarWorks@숙명여자대학교

초록

The increasing demand for recent applications such as deep learning, image processing, and post-quantum cryptography security algorithms has led to continuous growth in the amount of data requiring processing. Consequently, there is a renewed focus on developing lightweight designs for a fundamental arithmetic operation, multiplication, in this domain. In this paper, we propose a new approach to the radix-4 Booth multiplier that offers advantages in terms of power consumption and area. Constructing complex Boolean expressions with compound gates effectively reduced the number of transistors. Additionally, an efficient design was achieved by overlapping repetitive portions of the Boolean expressions. The proposed multiplier designed under the 28nm CMOS technology demonstrates a decrease in power consumption by 38.3% and a 44.3% reduction in transistor count. © 2023 IEEE.

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