ScholarWorks@숙명여자대학교

초록

This letter presents a periodically refreshed capacitive floating level shifter (CFLS) for applications that require a conditional switching signal. The proposed structure can generate a floating signal without additional bias voltage, and all coupling capacitors (CCs) can be simultaneously refreshed. Digital low-dropout (DLDOs) regulators are integrated to show how the leakage current from a CC affects the DLDOs that are driven by conventional and proposed CFLSs. Results are measured according to the temperature and supply voltage. With a 28-nm CMOS process, the proposed CFLS achieves a delay of 8.9 ns including the I/O buffer delay and an energy consumption of 788 fJ per cycle at V-DD = 0.9 V.

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