Hardware Implementation of On-Chip Hebbian Learning Through Integrated Neuromorphic Architecture

초록

The von Neumann bottleneck and growing energy demands of conventional computing systems require innovative architectural solutions. Although neuromorphic computing is a promising alternative, implementing efficient on-chip learning mechanisms remains a fundamental challenge. Herein, a novel artificial neural platform is presented that integrates three synergistic components: modulation-optimized presynaptic transistors, threshold switching memristor-based neurons, and adaptive feedback synapses. The platform demonstrates real-time synaptic weight modification through correlation-based learning, effectively implementing Hebbian principles in hardware without requiring extensive peripheral circuitry. Stable device operation and successful implementation of local learning rules are confirmed by systematically characterizing a 6 x 6 array configuration. The experimental results demonstrate a correlation between input-output signals and subsequent weight modifications, establishing a viable pathway toward hardware implementation of Hebbian learning in neuromorphic systems.

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