Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Yoonjin | - |
dc.date.available | 2021-02-22T13:15:46Z | - |
dc.date.issued | 2011-12 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/12440 | - |
dc.description.abstract | Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/ power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/ power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/ power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network. | - |
dc.format.extent | 11 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor | - |
dc.type | Article | - |
dc.publisher.location | 대한민국 | - |
dc.identifier.doi | 10.5573/JSTS.2011.11.4.318 | - |
dc.identifier.scopusid | 2-s2.0-84855453465 | - |
dc.identifier.wosid | 000301291600013 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.11, no.4, pp 318 - 328 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 11 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 318 | - |
dc.citation.endPage | 328 | - |
dc.type.docType | Article | - |
dc.identifier.kciid | ART001643963 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | AREA | - |
dc.subject.keywordAuthor | Chip multiprocessor (CMP) | - |
dc.subject.keywordAuthor | reconfigurable architecture | - |
dc.subject.keywordAuthor | interconnection | - |
dc.subject.keywordAuthor | fault-tolerant computing | - |
dc.subject.keywordAuthor | low power | - |
dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01754976&language=ko_KR | - |
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