Reconfigurable Multi-Array Architecture for Low-Power and High-Speed Embedded Systems
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Yoonjin | - |
dc.date.available | 2021-02-22T13:16:39Z | - |
dc.date.issued | 2011-09 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/12514 | - |
dc.description.abstract | Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures. | - |
dc.format.extent | 14 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Reconfigurable Multi-Array Architecture for Low-Power and High-Speed Embedded Systems | - |
dc.type | Article | - |
dc.publisher.location | 대한민국 | - |
dc.identifier.doi | 10.5573/JSTS.2011.11.3.207 | - |
dc.identifier.scopusid | 2-s2.0-83055170749 | - |
dc.identifier.wosid | 000301290800009 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.11, no.3, pp 207 - 220 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 11 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 207 | - |
dc.citation.endPage | 220 | - |
dc.type.docType | Article | - |
dc.identifier.kciid | ART001643893 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | Embedded systems | - |
dc.subject.keywordAuthor | Coarse-Grained Reconfigurable Architecture (CGRA) | - |
dc.subject.keywordAuthor | computing hierarchy | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | high performance | - |
dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01777749&language=ko_KR | - |
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