A Digital FLL-based Sub-harmonically Injection-locked PLL with Resolution-multiplied TDC for Frequency Offset Cancellation
DC Field | Value | Language |
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dc.contributor.author | An, Jong Chan | - |
dc.contributor.author | Yu, Seung-Myeong | - |
dc.contributor.author | Jeong, Jun Won | - |
dc.contributor.author | Song, Jun Young | - |
dc.date.accessioned | 2023-11-08T05:50:07Z | - |
dc.date.available | 2023-11-08T05:50:07Z | - |
dc.date.issued | 2023-06 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/151752 | - |
dc.description.abstract | This paper presents the implementation of a Resolution-Multiplied Time-to-Digital Converter (RM-TDC) and a Sub-harmonically Injection locked Phase-Locked Loop (SIPLL) based on a digital frequency loop to correct frequency offset. The proposed design performs frequency adjustment via a Sampled-Edge-Direction-Dependent Frequency Detector (SEDD-FD), achieving faster and more efficient frequency lock. Also, RM-TDC was used to detect the frequency offset in order to enhance jitter performance. This design has an integrated jitter of 676 fs, a phase noise of -114.26 dBc/Hz at 10 Mhz, occupies an area of 0.052 mm2, and consumes 2.43 mW. It is manufactured using a 65 nm CMOS process. | - |
dc.format.extent | 4 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | 대한전자공학회 | - |
dc.title | A Digital FLL-based Sub-harmonically Injection-locked PLL with Resolution-multiplied TDC for Frequency Offset Cancellation | - |
dc.title.alternative | A Digital FLL-based Sub-harmonically Injection-locked PLL with Resolution-multiplied TDC for Frequency Offset Cancellation | - |
dc.type | Article | - |
dc.publisher.location | 대한민국 | - |
dc.identifier.doi | 10.5573/JSTS.2023.23.3.202 | - |
dc.identifier.scopusid | 2-s2.0-85165734974 | - |
dc.identifier.wosid | 001030895600004 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.23, no.3, pp 202 - 205 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 23 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 202 | - |
dc.citation.endPage | 205 | - |
dc.type.docType | Article | - |
dc.identifier.kciid | ART002967682 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | Injection-locking | - |
dc.subject.keywordAuthor | digital FLL | - |
dc.subject.keywordAuthor | time-to-digital-converter | - |
dc.subject.keywordAuthor | wireline communication | - |
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