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Reconfigurable hardware architecture for faster descriptor extraction in SURF

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dc.contributor.authorKim, Y.-
dc.contributor.authorJung, H.-
dc.date.available2021-02-22T09:46:12Z-
dc.date.issued2018-02-
dc.identifier.issn0013-5194-
dc.identifier.issn1350-911X-
dc.identifier.urihttps://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/4719-
dc.description.abstractSpeeded up robust features (SURFs) are considered to be the most efficient feature extraction algorithm and it has been implemented in powerful hardware for real-time operation due to its characteristics of data-intensive computation of high complexity. Especially, the computational load of the descriptor extraction procedure is very significant and the overall performance of SURF can be improved by speeding up the descriptor extraction step with increasing parallel hardware accelerators. However, simply increasing the hardware accelerators is burdensome because of causing significant area and power consumption. Therefore, a reconfigurable hardware architecture is proposed that enables achieving the maximum performance of the descriptor extraction step with making the best use of the existing accelerators without any additional ones. Experimental results show that the proposed architecture improves the performance of the descriptor extraction step by 24.77-47.45% with negligible area overheads when compared with the existing hardware implementations of the SURF algorithm.-
dc.format.extent3-
dc.language영어-
dc.language.isoENG-
dc.publisherINST ENGINEERING TECHNOLOGY-IET-
dc.titleReconfigurable hardware architecture for faster descriptor extraction in SURF-
dc.typeArticle-
dc.publisher.location영국-
dc.identifier.doi10.1049/el.2017.3133-
dc.identifier.scopusid2-s2.0-85042527205-
dc.identifier.wosid000425765100016-
dc.identifier.bibliographicCitationELECTRONICS LETTERS, v.54, no.4, pp 210 - 212-
dc.citation.titleELECTRONICS LETTERS-
dc.citation.volume54-
dc.citation.number4-
dc.citation.startPage210-
dc.citation.endPage212-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordAuthorreal-time systems-
dc.subject.keywordAuthorfeature extraction-
dc.subject.keywordAuthorreconfigurable architectures-
dc.subject.keywordAuthorreconfigurable hardware architecture-
dc.subject.keywordAuthordescriptor extraction procedure-
dc.subject.keywordAuthorspeeded up robust features-
dc.subject.keywordAuthorfeature extraction algorithm-
dc.subject.keywordAuthorreal-time operation-
dc.subject.keywordAuthordata-intensive computation-
dc.subject.keywordAuthorcomputational load-
dc.subject.keywordAuthorparallel hardware accelerators-
dc.subject.keywordAuthorSURF algorithm-
dc.identifier.urlhttps://digital-library.theiet.org/content/journals/10.1049/el.2017.3133-
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공과대학 (소프트웨어학부(첨단))
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