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An Output Capacitorless Low-Dropout Regulator With a Low-V-DD Inverting Buffer for the Mobile Application

Authors
Park, JieunLee, ByunghunHong, Sung-Wan
Issue Date
Nov-2019
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Buffer; capacitorless; low-dropout regulator (LDO); low-V-DD structure; power supply rejection ratio (PSRR)
Citation
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, v.67, no.10, pp.8931 - 8935
Journal Title
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume
67
Number
10
Start Page
8931
End Page
8935
URI
https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/1166
DOI
10.1109/TIE.2019.2951296
ISSN
0278-0046
Abstract
To provide power to the latest mobile applications that use functions with heavy loads, in this letter, we present a capacitorless low-dropout regulator (LDO) that supplies a large load current up to 600 mA. The proposed buffer and the feedforward paths are used to provide a stable operation and fast response along with a large load current. Owing to these schemes, the proposed LDO has a high unity gain frequency of 2.85 MHz at 100 mA with a total compensation capacitance of 5.1 pF. In addition, the LDO operates under a wide input voltage range of 1.5-5.0 V owing to the low-V-DD structure. Also, a power supply rejection ratio was -52 dB at 100 kHz. The chip was implemented with a small size of 0.082 mm(2) using the I/O devices of a 0.18 mu m CMOS process with a minimum length of 0.5 mu m.
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