A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping
- Authors
- Park, D (Park, Dongchul); Debnath, B (Debnath, Biplob); Du, DHC (Du, David H. C.)
- Issue Date
- Jun-2016
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Citation
- IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E99D, no.6, pp 1502 - 1511
- Pages
- 10
- Journal Title
- IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
- Volume
- E99D
- Number
- 6
- Start Page
- 1502
- End Page
- 1511
- URI
- https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/147055
- DOI
- 10.1587/transinf.2015EDP7406
- ISSN
- 0916-8532
1745-1361
- Abstract
- The Flash Translation Layer ( FTL) is a firmware layer inside NAND flash memory that allows existing disk-based applications to use it without any significant modifications. Since the FTL has a critical impact on the performance and reliability of flash-based storage, a variety of FTLs have been proposed. The existing FTLs, however, are designed to perform well for either a read intensive workload or a write intensive workload, not for both due to their internal address mapping schemes. To overcome this limitation, we propose a novel hybrid FTL scheme named Convertible Flash Translation Layer ( CFTL). CFTL is adaptive to data access patterns with the help of our unique hot data identification design that adopts multiple bloom filters. Thus, CFTL can dynamically switch its mapping scheme to either page-level mapping or block-level mapping to fully exploit the benefits of both schemes. In addition, we design a spatial locality-aware caching mechanism and adaptive cache partitioning to further improve CFTL performance. Consequently, both the adaptive switching scheme and the judicious caching mechanism empower CFTL to achieve good read and write performance. Our extensive evaluations demonstrate that CFTL outperforms existing FTLs. In particular, our specially designed caching mechanism remarkably improves the cach
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