Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chung, Jinil | - |
dc.contributor.author | Choi, Woong | - |
dc.contributor.author | Park, Jongsun | - |
dc.contributor.author | Ghosh, Swaroop | - |
dc.date.available | 2021-02-22T05:35:53Z | - |
dc.date.issued | 2020-01 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/2566 | - |
dc.description.abstract | In the hardware implementation of deep learning algorithms such as, convolutional neural networks (CNNs) and binarized neural networks (BNNs), multiple dot products and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a domain wall memory (DWM) based design of CNN and BNN convolutional layers. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and energy cost of DWM-based design for filter sliding. Simulation results with 65 nm CMOS process show 45% and 43% of energy savings compared to the conventional CNN and BNN design approach, respectively. | - |
dc.format.extent | 16 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/ACCESS.2020.2968081 | - |
dc.identifier.scopusid | 2-s2.0-85079754546 | - |
dc.identifier.wosid | 000525389200009 | - |
dc.identifier.bibliographicCitation | IEEE ACCESS, v.8, pp 19783 - 19798 | - |
dc.citation.title | IEEE ACCESS | - |
dc.citation.volume | 8 | - |
dc.citation.startPage | 19783 | - |
dc.citation.endPage | 19798 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordAuthor | Binarized neural network | - |
dc.subject.keywordAuthor | convolutional neural network | - |
dc.subject.keywordAuthor | deep neural network | - |
dc.subject.keywordAuthor | domain wall memory | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8963965 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
Sookmyung Women's University. Cheongpa-ro 47-gil 100 (Cheongpa-dong 2ga), Yongsan-gu, Seoul, 04310, Korea02-710-9127
Copyright©Sookmyung Women's University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.