Impact of Heat Treatment on a Hetero-Stacked MoS2/h-BN Field-Effect Transistor
DC Field | Value | Language |
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dc.contributor.author | Ji, Hyunjin | - |
dc.contributor.author | Yi, Hojoon | - |
dc.contributor.author | Nguyen, Huong Thi Thanh | - |
dc.contributor.author | Wonkil, Sakong | - |
dc.contributor.author | Joo, Min-Kyu | - |
dc.contributor.author | Kim, Hyun | - |
dc.contributor.author | Lim, Seong Chu | - |
dc.date.available | 2021-02-22T05:45:34Z | - |
dc.date.issued | 2019-10 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.issn | 1558-0563 | - |
dc.identifier.uri | https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/2786 | - |
dc.description.abstract | We investigated device properties before and after heat treatment for a hetero-stacked two-dimensional field-effect transistor (FET). In dual-gated monolayer MoS2 FET using a top h-BN layer and bottom SiO2 substrate, careful but harsh heat treatment is implemented in high vacuum at 200 similar to C for 18 h. Under the top-gate bias sweep, the field-effect mobility increases by similar to 9 times, and the channel carrier density doubles after the treatment. The heat treatment effect is more noticeable in the top-transferred h-BN than in the bottom SiO2 layer, because it leads to homogeneous adhesion between the layers by diminishing the adverse effects of interfacial bubbles or adsorbates. A top-gate dielectric capacitance for h-BN of 55 fF is increased to similar to 70 fF after the treatment, which is comparable to the theoretical value. This indicates that strong capacitive coupling for the top gate is formed, as confirmed by the capacitance-voltage measurement. | - |
dc.format.extent | 4 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Impact of Heat Treatment on a Hetero-Stacked MoS2/h-BN Field-Effect Transistor | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/LED.2019.2936233 | - |
dc.identifier.scopusid | 2-s2.0-85077740785 | - |
dc.identifier.wosid | 000489740400015 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.40, no.10, pp 1626 - 1629 | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 40 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 1626 | - |
dc.citation.endPage | 1629 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | sci | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | HEXAGONAL BORON-NITRIDE | - |
dc.subject.keywordPlus | HETEROSTRUCTURES | - |
dc.subject.keywordPlus | GRAPHENE | - |
dc.subject.keywordPlus | LAYERS | - |
dc.subject.keywordAuthor | Intensive heat treatment | - |
dc.subject.keywordAuthor | monolayer MoS2 | - |
dc.subject.keywordAuthor | dual-gate FET | - |
dc.subject.keywordAuthor | capacitive coupling | - |
dc.subject.keywordAuthor | interfacial adsorbates | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8813125 | - |
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