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A Pseudo Single-Stage Amplifier With an Adaptively Varied Medium Impedance Node for Ultra-High Slew Rate and Wide-Range Capacitive-Load Drivability

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dc.contributor.authorHong, Sung-Wan-
dc.contributor.authorCho, Gyu-Hyeong-
dc.date.available2021-02-22T06:13:09Z-
dc.date.created2021-01-29-
dc.date.issued2016-09-
dc.identifier.issn1549-8328-
dc.identifier.urihttps://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/3231-
dc.description.abstractThis paper presents a pseudo single-stage (PSS) amplifier with an adaptively varied medium impedance node to achieve an ultra-high slew rate (SR) and at the same time stable operation in a wide capacitive load range. Owing to the characteristics of the proposed technique, this amplifier achieves a 1.1-to-8.67 V/μs slew rate and a 0.01-to-1.66 MHz unity gain frequency over a 0.1-to-15 nF capacitive load (C L ) with an over 69° phase margin while consuming a total quiescent power of only 7.4 μW. This chip was fabricated in a 0.18 μm CMOS process with a silicon area of 0.0021 mm 2 .-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA Pseudo Single-Stage Amplifier With an Adaptively Varied Medium Impedance Node for Ultra-High Slew Rate and Wide-Range Capacitive-Load Drivability-
dc.typeArticle-
dc.contributor.affiliatedAuthorHong, Sung-Wan-
dc.identifier.doi10.1109/TCSI.2016.2584919-
dc.identifier.scopusid2-s2.0-84988667056-
dc.identifier.wosid000385621800002-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.10, pp.1567 - 1578-
dc.relation.isPartOfIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.citation.titleIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.citation.volume63-
dc.citation.number10-
dc.citation.startPage1567-
dc.citation.endPage1578-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusNESTED-MILLER COMPENSATION-
dc.subject.keywordPlus3-STAGE AMPLIFIER-
dc.subject.keywordPlusFREQUENCY COMPENSATION-
dc.subject.keywordPlusMULTISTAGE AMPLIFIERS-
dc.subject.keywordPlusBUFFER AMPLIFIER-
dc.subject.keywordPlusDRIVERS-
dc.subject.keywordPlusTIME-
dc.subject.keywordAuthorAdaptively varied medium impedance-
dc.subject.keywordAuthorhigh slew rate-
dc.subject.keywordAuthorpole-zero doublets-
dc.subject.keywordAuthorpseudo single-stage-
dc.subject.keywordAuthorwide-range capacitive load drivability-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/7571153-
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