A Digital FLL-based Sub-harmonically Injection-locked PLL with Resolution-multiplied TDC for Frequency Offset CancellationA Digital FLL-based Sub-harmonically Injection-locked PLL with Resolution-multiplied TDC for Frequency Offset Cancellation
- Other Titles
- A Digital FLL-based Sub-harmonically Injection-locked PLL with Resolution-multiplied TDC for Frequency Offset Cancellation
- Authors
- An, Jong Chan; Yu, Seung-Myeong; Jeong, Jun Won; Song, Jun Young
- Issue Date
- Jun-2023
- Publisher
- 대한전자공학회
- Keywords
- Injection-locking; digital FLL; time-to-digital-converter; wireline communication
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.23, no.3, pp 202 - 205
- Pages
- 4
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 23
- Number
- 3
- Start Page
- 202
- End Page
- 205
- URI
- https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/151752
- DOI
- 10.5573/JSTS.2023.23.3.202
- ISSN
- 1598-1657
2233-4866
- Abstract
- This paper presents the implementation of a Resolution-Multiplied Time-to-Digital Converter (RM-TDC) and a Sub-harmonically Injection locked Phase-Locked Loop (SIPLL) based on a digital frequency loop to correct frequency offset. The proposed design performs frequency adjustment via a Sampled-Edge-Direction-Dependent Frequency Detector (SEDD-FD), achieving faster and more efficient frequency lock. Also, RM-TDC was used to detect the frequency offset in order to enhance jitter performance. This design has an integrated jitter of 676 fs, a phase noise of -114.26 dBc/Hz at 10 Mhz, occupies an area of 0.052 mm2, and consumes 2.43 mW. It is manufactured using a 65 nm CMOS process.
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Collections - ICT융합공학부 > 전자공학전공 > 1. Journal Articles
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