<inline-formula> <tex-math notation=LaTeX>$\mathbf{T^3L}$</tex-math> </inline-formula>: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure
- Authors
- Kim, Jongbeom; Lee, Hyundong; Ko, Jonghyun; Kim, Bong Jun; Song, Taigon
- Issue Date
- Dec-2023
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- anti-ambipolar transistor (AAT); CNTFETs; Design methodology; Multi-valued logic; Multivalued logic; Power demand; Resistance; Symbols; ternary full-adder; ternary logic; Transistors
- Citation
- IEEE Transactions on Circuits and Systems I: Regular Papers, v.70, no.12, pp 1 - 14
- Pages
- 14
- Journal Title
- IEEE Transactions on Circuits and Systems I: Regular Papers
- Volume
- 70
- Number
- 12
- Start Page
- 1
- End Page
- 14
- URI
- https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/159756
- DOI
- 10.1109/TCSI.2023.3311034
- ISSN
- 1549-8328
1558-0806
- Abstract
- The imminent rise in data consumption and the physical constraints of current advanced CMOS scaling hasten the end of the projection to the binary system. For a breakthrough of these issues, the ternary system, known for its superior efficiency in expressing numbers (closest to <inline-formula> <tex-math notation=LaTeX>$\mathrm{e}\approx$</tex-math> </inline-formula> 2.7183) has garnered considerable attention. Among the ternary studies reported, the anti-ambipolar transistor (AAT) is acquiring attention thanks to its unique negative differential resistance (NDR) and anti-ambipolar characteristics (AAC). Moreover, easy-to-fabricate inkjet-printing based AAT was introduced. Therefore, in this paper, we propose a practical design methodology (‘<inline-formula> <tex-math notation=LaTeX>$\mathbf{T^3L:} $</tex-math> </inline-formula> <bold>The Tri-transistor Ternary Logic</bold>’) and a set of novel ternary logic based on inkjet-printed AATs and CMOSs. In detail, 1) We propose balanced ternary full adders (BTFA) and prove that inkjet-printed AATs and CMOSs are highly capable of implementing any kind of ternary logic. 2) We propose two design methodologies for ternary logic design: NDR-based Design Method I and AAC-based Design Method II. 3) We present optimization methodology for inkjet-printed ternary circuit stability and provide circuitry to secure sufficient noise margin. We provide a highly-compact BTFA design that requires only 64 transistors and an ultra-low-power BTFA design that reduces power by 84.7% to 98.8% compared to the previous designs. IEEE
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