Low Cost Convolutional Neural Network Accelerator Based on Bi-Directional Filtering and Bit-Width Reduction
- Authors
- Choi, Woong; Choi, Kyungrak; Park, Jongsun
- Issue Date
- Mar-2018
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Citation
- IEEE Access, v.6, pp 14734 - 14746
- Pages
- 13
- Journal Title
- IEEE Access
- Volume
- 6
- Start Page
- 14734
- End Page
- 14746
- URI
- https://scholarworks.sookmyung.ac.kr/handle/2020.sw.sookmyung/146937
- DOI
- 10.1109/ACCESS.2018.2816019
- ISSN
- 2169-3536
- Abstract
- This paper presents a low-area and energy-efficient hardware accelerator for the convolutional neural networks (CNNs). Based on the multiply-accumulate-based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational cost of convolutions, an adaptive bit-width reduction combined with near-zero skipping is proposed based on differential input method (DIM). The DIM-based design technique can reduce 62.5% of operation bit-width and improve 17.0% of activation sparsity with almost ignorable CNN accuracy degradation. Second, it has been found that adopting a bi-directional filtering window in a CNN accelerator can considerably reduce the energy for data movement with a much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bi-directional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 34.6% and 58.2% of area and energy savings, respectively. The bi-FIFO-based accelerator also
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